Partially recessed channel core transistors in replacement gate flow

ABSTRACT

An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. Moreparticularly, this invention relates to MOS transistors in integratedcircuits.

BACKGROUND OF THE INVENTION

An integrated circuit may include metal oxide semiconductor (MOS)transistors formed using a gate replacement process. It may be desirableto increase threshold uniformity in a portion of the MOS transistorswithout increasing the area occupied by the transistors.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to amore detailed description that is presented later.

An integrated circuit containing MOS transistors with replacement gatesmay be formed with elevated LDD regions and/or recessed replacementgates on a portion of the transistors. Elevating the LDD regions isaccomplished by a selective epitaxial process prior to LDD implant.Recessing the replacement gates is accomplished by etching substratematerial after removal of sacrificial gate material and before formationof a replacement gate dielectric layer. Elevating the LDD regions andrecessing the replacement gates may increase a channel length of the MOStransistors and thereby desirably increase threshold uniformity of thetransistors.

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1A through FIG. 1H are cross sections of an integrated circuit,depicted in successive stages of fabrication.

FIG. 2 is a cross section of an integrated circuit containing an MOStransistor with elevated LDD regions.

FIG. 3 is a cross section of an integrated circuit containing an MOStransistor with a recessed replacement gate.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The present invention is described with reference to the attachedfigures. The figures are not drawn to scale and they are provided merelyto illustrate the invention. Several aspects of the invention aredescribed below with reference to example applications for illustration.It should be understood that numerous specific details, relationships,and methods are set forth to provide an understanding of the invention.One skilled in the relevant art, however, will readily recognize thatthe invention can be practiced without one or more of the specificdetails or with other methods. In other instances, well-known structuresor operations are not shown in detail to avoid obscuring the invention.The present invention is not limited by the illustrated ordering of actsor events, as some acts may occur in different orders and/orconcurrently with other acts or events. Furthermore, not all illustratedacts or events are required to implement a methodology in accordancewith the present invention.

An integrated circuit containing MOS transistors with replacement gatesmay be formed with elevated LDD regions and/or recessed replacementgates on a portion of the transistors, so that channels and gatedielectric layers extend along both horizontal and vertical surfaces.Elevating the LDD regions is accomplished by a selective epitaxialprocess prior to LDD implant. Recessing the replacement gates isaccomplished by etching substrate material after removal of sacrificialgate material and before formation of a replacement gate dielectriclayer. Elevating the LDD regions and recessing the replacement gates mayincrease a channel length of the MOS transistors and thereby desirablyincrease threshold uniformity of the transistors without increasing areaoccupied by the transistors.

FIG. 1A through FIG. 1H are cross sections of an integrated circuit,depicted in successive stages of fabrication. Referring to FIG. 1A, theintegrated circuit 100 is formed in and on a semiconductor substrate102, which may be a single crystal silicon wafer, a silicon-on-insulator(SOI) wafer, a hybrid orientation technology (HOT) wafer with regions ofdifferent crystal orientations, or other material appropriate forfabrication of the integrated circuit 100.

Field oxide 104 is formed at a top surface of the substrate 102. Thefield oxide 104 may be, for example, silicon dioxide between 200 and 400nanometers thick, formed by a shallow trench isolation (STI) process. AnSTI process may include the steps of: forming an oxide layer on thesubstrate 102, forming a silicon nitride layer on the oxide layer,patterning the silicon nitride layer so as to expose an area for thefield oxide 104, etching a trench in the substrate 102 in the exposedarea to an appropriate depth for a desired thickness of the field oxide104, growing a layer of thermal oxide on sidewalls and a bottom of thetrench, filling the trench with silicon dioxide by chemical vapordeposition (CVD), high density plasma (HDP) or high aspect ratio process(HARP), removing unwanted silicon dioxide from a top surface of thesilicon nitride layer, and removing the silicon nitride layer.

The field oxide 104 laterally isolates a first MOS transistor 106 from asecond MOS transistor 108. The first MOS transistor 106 and the secondMOS transistor 108 have a same polarity. The first MOS transistor 106may be part of a circuit requiring a narrow range of thresholdpotentials, such as a static random access memory (SRAM) circuit, or anamplifier circuit. The second MOS transistor 108 may be part of acircuit which may tolerate a wider range of threshold potentials, suchas a logic circuit or multiplexer.

The first MOS transistor 106 includes a first sacrificial gatedielectric layer 110 formed at the top surface of the substrate 102, anda first sacrificial gate 112 formed over the first sacrificial gatedielectric layer 110. First offset spacers 114 may be formed on lateralsurfaces of the first sacrificial gate 112. Similarly, the second MOStransistor 108 includes a second sacrificial gate dielectric layer 116formed at the top surface of the substrate 102, and a second sacrificialgate 118 formed over the second sacrificial gate dielectric layer 116.Second offset spacers 120 may be formed on lateral surfaces of thesecond sacrificial gate 118. In one version of the instant embodiment, afirst gate linewidth 122 of the first sacrificial gate 112 issubstantially equal to a second gate linewidth 124 of the secondsacrificial gate 118. The term “gate linewidth” is to be understood forthe purposes of this disclosure to refer to a lateral width of a in adirection of current flow in an MOS transistor containing the gate.

In an alternate version, the first gate linewidth 122 of the firstsacrificial gate 112 is 80 to 90 percent of the second gate linewidth124 of the second sacrificial gate 118.

The first sacrificial gate dielectric layer 110 and the secondsacrificial gate dielectric layer 116 may be, for example, 1 to 10nanometers of silicon dioxide which is deposited or thermally grown. Thefirst sacrificial gate 112 and the second sacrificial gate 118 may be,for example, polycrystalline silicon, commonly referred to aspolysilicon, patterned using a hard mask and a reactive ion etch (RIE)process. The first offset spacers 114 and second offset spacers 120 maybe, for example, 1 to 10 nanometers of silicon nitride, conformallydeposited by plasma enhanced chemical vapor deposition (PECVD) usingammonia and bis (tertiary-butylamino) silane (BTBAS).

An epi-block layer 126 is formed over the second MOS transistor 108 soas to cover the top surface of the substrate 102 adjacent to the secondsacrificial gate 118. The epi-block layer 126 may be, for example, 10 to50 nanometers of silicon dioxide, conformally deposited by PECVD usingoxygen and tetraethyl orthosilicate, also known as tetraethoxysilane orTEOS. The epi-block layer 126 is patterned so as to expose the first MOStransistor 106.

Referring to FIG. 1B, a selective epitaxial growth process is performedwhich forms elevated LDD semiconductor regions 128 of semiconductormaterial, for example, crystalline silicon, on the substrate 102adjacent to the first sacrificial gate 112. The selective epitaxialgrowth process may include reduction of silane, dichlorosilane ortetrachlorosilane by hydrogen and hydrogen chloride at 800° C. to 1200°C. A top surface of the elevated LDD semiconductor regions 128 may be,for example, 2 to 10 nanometers above the top surface of the substrate102. Significant amounts of semiconductor material are not formed on thefield oxide 104 or the epi-block layer 126 by the selective epitaxialgrowth process.

Referring to FIG. 1C, the epi-block layer 126 is removed, for exampleusing an RIE process with a fluorine-containing plasma. Subsequently, anLDD implant process is performed which implants dopants into theelevated LDD semiconductor regions 128 in the first MOS transistor 106to form first LDD implanted regions 130. Concurrently, the LDD implantprocess implants the dopants into the substrate 102 adjacent to thesecond sacrificial gate 118 to form second LDD implanted regions 132 inthe second MOS transistor 108.

Referring to FIG. 1D, the integrated circuit 100 is annealed so that thedopants in the first LDD implanted regions 130 and the second LDDimplanted regions 132 are activated so as to form elevated first LDDregions 134 and second LDD regions 136 in the substrate 102 adjacent tothe first sacrificial gate 112 and the second sacrificial gate 118,respectively. A top surface of the elevated first LDD regions 134 maybe, for example, 2 to 10 nanometers above the top surface of thesubstrate 102. Source/drain spacers 138 are formed adjacent to the firstsacrificial gate 112 and the second sacrificial gate 118. Thesource/drain spacers 138 may be, for example, 10 to 30 nanometers ofsilicon dioxide.

First epitaxial source and drain regions 140 and second epitaxial sourceand drain regions 142 may be formed in the first MOS transistor 106 andthe second MOS transistor 108, respectively. The first epitaxial sourceand drain regions 140 and the second epitaxial source and drain regions142 may be formed, for example, by removing semiconductor material fromthe elevated LDD semiconductor regions 128 and the substrate 102adjacent to the source/drain spacers 138, and forming epitaxialsemiconductor material with a different stoichiometry in the regionwhere the semiconductor material from the elevated LDD semiconductorregions 128 and the substrate 102 was removed. The elevated first LDDregions 134 provide drain extensions for the first epitaxial source anddrain regions 140; similarly, the second LDD regions 136 provide drainextensions for the second epitaxial source and drain regions 142.

Referring to FIG. 1E, a dielectric layer 144 is formed over theintegrated circuit 100 so as to cover areas adjacent to the firstsacrificial gate 112 and the second sacrificial gate 118 and to exposetop surfaces of the first sacrificial gate 112 and the secondsacrificial gate 118. The dielectric layer 144 may be formed, forexample, by depositing a conformal layer of silicon dioxide by PECVDusing TEOS or a spin-on process using methylsilsesquioxane (MSQ), or bydepositing silicon dioxide using an HDP process. The conformal layer ofsilicon dioxide may subsequently be planarized using a chemicalmechanical polish (CMP) process and/or an etchback process such as aresist etchback process, so as to expose the top surfaces of the firstsacrificial gate 112 and the second sacrificial gate 118 while leavingthe dielectric layer 144 covering the areas adjacent to the firstsacrificial gate 112 and the second sacrificial gate 118.

Referring to FIG. 1F, the first sacrificial gate 112 and the secondsacrificial gate 118 of FIG. 1E are removed, for example using a dryetch or a wet etch that is selective to the first sacrificial gatedielectric layer 110 and the second sacrificial gate dielectric layer116. Subsequently, the first sacrificial gate dielectric layer 110 andthe second sacrificial gate dielectric layer 116 of FIG. 1E are removed,for example using another dry etch or a wet etch that is selective tothe substrate 102. The first offset spacers 114 and second offsetspacers 120 of FIG. 1E may also be removed, for example using anisotropic plasma etch that is selective to the source/drain spacers 138.

Referring to FIG. 1G, an etch mask 146 is formed over the substrate 102in the second MOS transistor 108 located under the second sacrificialgate 118 of FIG. 1E, so as to expose the substrate 102, and possibly thefield oxide 104, in the first MOS transistor 106 located under the firstsacrificial gate 112 of FIG. 1E. The etch mask 146 may include, forexample, photoresist and be formed by a photolithographic process.

Subsequently, a gate recess etch is performed which removessemiconductor material from the substrate 102, and the field oxide 104if exposed, located under the first sacrificial gate 112. The gaterecess etch is performed so that an etched surface of the substrate 102is substantially coplanar with an etched surface of the field oxide 104.The gate recess etch is further performed so that divots are avoided,for example at edges of the source/drain spacers 138 and at boundariesbetween the field oxide 104 and the substrate 102. The gate recess etchmay, for example, include a plasma using CF₄ and argon, and optionallyO₂. Another possible gate recess etch may include a plasma using SF₆, O₂and argon. The gate recess etch may be performed in two steps, in whichthe substrate 102 is etched faster than the field oxide 104 in one stepand vice versa in another step. O₂ flow may be adjusted to attain adesired etch rate of the substrate 102. In an alternate version of theinstant embodiment, the gate recess etch may include, for example, anisotropic plasma etch using NF₃, SF₆ and CHF₃. In one version of theinstant embodiment, 2 to 50 nanometers of semiconductor material may beremoved. In another version, 3 to 10 nanometers of semiconductormaterial may be removed. The etch mask 146 is removed after the gaterecess etch is completed.

Referring to FIG. 1H, a first replacement gate dielectric layer 148 anda second replacement gate dielectric layer 150 are formed concurrentlyon the substrate 102 in the first MOS transistor 106 and the second MOStransistor 108, respectively. A surface of the substrate 102 under thefirst replacement gate dielectric layer 148 is substantially coplanarwith a surface of the field oxide under the first replacement gatedielectric layer 148. The first replacement gate dielectric layer 148and the second replacement gate dielectric layer 150 have substantiallyequal composition. Subsequently, a recessed first replacement gate 152and a second replacement gate 154 are formed concurrently on the firstreplacement gate dielectric layer 148 and the second replacement gatedielectric layer 150, respectively. In one version of the instantembodiment, the recessed first replacement gate 152 is recessed 2 to 50nanometers below the top surface of the substrate 102. In anotherversion, the recessed first replacement gate 152 is recessed 3 to 10nanometers. The recessed first replacement gate 152 and the secondreplacement gate 154 have substantially equal composition and structure.The recessed first replacement gate dielectric layer 148 and the secondreplacement gate dielectric layer 150 may have, for example, highdielectric coefficients and include tantalum oxide, hafnium oxide and/orzirconium oxide. The recessed first replacement gate 152 and the secondreplacement gate 154 may include, for example, titanium nitride. Thefirst replacement gate dielectric layer 148, the second replacement gatedielectric layer 150, the recessed first replacement gate 152 and thesecond replacement gate 154 may be formed, for example, by depositing aconformal layer of gate dielectric material, depositing replacement gatematerial on the layer of gate dielectric material, and subsequentlyremoving the gate dielectric material and the replacement gate materialfrom over the dielectric layer 144. In one version of the instantembodiment, a first replacement gate linewidth 156 of the recessed firstreplacement gate 152 is substantially equal to a second replacement gatelinewidth 158 of the second replacement gate 154. In an alternateversion, the first replacement gate linewidth 156 of the recessed firstreplacement gate 152 is 80 to 90 percent of the second replacement gatelinewidth 158 of the second replacement gate 154.

A channel length of the first MOS transistor 106 is longer than achannel length of the second MOS transistor 108, due to the elevatedfirst LDD regions 134 and the recessed first replacement gate 152, whichmay desirably provide the first MOS transistor 106 with a thresholdpotential closer to a desired value than the second MOS transistor 108.A channel of the first MOS transistor 106 is extends along both ahorizontal and a vertical surface; a channel of the second MOStransistor 108 extends along a horizontal surface and not a verticalsurface.

FIG. 2 is a cross section of an integrated circuit containing an MOStransistor with elevated LDD regions. The integrated circuit 200 isformed in and on a semiconductor substrate 202, for example as describedin reference to FIG. 1A. Field oxide 204 is formed at a top surface ofthe substrate 202, for example as described in reference to FIG. 1A. Theintegrated circuit 200 includes a first MOS transistor 206 and a secondMOS transistor 208. The first MOS transistor 206 and the second MOStransistor 208 have a same polarity.

The first MOS transistor 206 includes elevated first LDD regions 234,formed for example as described in reference to the elevated first LDDregions 134 of FIG. 1A through FIG. 1D. The second MOS transistor 208includes second LDD regions 236 which are not elevated, formed forexample as described in reference to the second LDD regions 136 of FIG.1A through FIG. 1D.

The first MOS transistor 206 may include first epitaxial source anddrain regions 240 and the second MOS transistor may include secondepitaxial source and drain regions 242, formed concurrently as describedin reference to FIG. 1D. The first MOS transistor 206 includes a firstreplacement gate dielectric layer 248 on the substrate 202 and a firstreplacement gate 252 formed on the first replacement gate dielectriclayer 248. The second MOS transistor 208 includes a second replacementgate dielectric layer 250 on the substrate 202 and a second replacementgate 254 formed on the second replacement gate dielectric layer 250. Thefirst replacement gate 252 and the second replacement gate 254 are notrecessed. The first replacement gate dielectric layer 248, the secondreplacement gate dielectric layer 250, the first replacement gate 252and the second replacement gate 254 may be formed, for example, asdescribed in reference to the second replacement gate dielectric layer250 and the second replacement gate 254 of FIG. 1H. In one version ofthe instant embodiment, a first replacement gate linewidth 256 of thefirst replacement gate 252 is substantially equal to a secondreplacement gate linewidth 258 of the second replacement gate 254. In analternate version, the first replacement gate linewidth 256 of the firstreplacement gate 252 is 80 to 90 percent of the second replacement gatelinewidth 258 of the second replacement gate 254.

A channel length of the first MOS transistor 206 is longer than achannel length of the second MOS transistor 208, due to the elevatedfirst LDD regions 234, which may desirably provide the first MOStransistor 206 with a threshold potential closer to a desired value thanthe second MOS transistor 208. Forming the first MOS transistor 206 withthe elevated first LDD regions 234 and without a recessed replacementgate may provide a desired threshold value for the first MOS transistor206 while providing a desired cost and complexity of a fabricationsequence for the integrated circuit 200.

FIG. 3 is a cross section of an integrated circuit containing an MOStransistor with a recessed replacement gate. The integrated circuit 300is formed in and on a semiconductor substrate 302, for example asdescribed in reference to FIG. 1A. Field oxide 304 is formed at a topsurface of the substrate 302, for example as described in reference toFIG. 1A. The integrated circuit 300 includes a first MOS transistor 306and a second MOS transistor 308. The first MOS transistor 306 and thesecond MOS transistor 308 have a same polarity.

The first MOS transistor 306 includes first LDD regions 334 which arenot elevated and the second MOS transistor 308 includes second LDDregions 336 which are not elevated, formed for example as described inreference to the second LDD regions 136 of FIG. 1C and FIG. 1D. Thefirst MOS transistor 306 may include first epitaxial source and drainregions 340 and the second MOS transistor may include second epitaxialsource and drain regions 342, formed concurrently as described inreference to FIG. 1D.

The first MOS transistor 306 includes a first replacement gatedielectric layer 348 and a recessed first replacement gate 352 formed onthe first replacement gate dielectric layer 348. The first replacementgate dielectric layer 348 and the recessed first replacement gate 352may be formed, for example, as described in reference to the firstreplacement gate dielectric layer 148 and the recessed first replacementgate 152 of FIG. 1G and FIG. 1H. The second MOS transistor 308 includesa second replacement gate dielectric layer 350 on the substrate 302 anda second replacement gate 354 formed on the second replacement gatedielectric layer 350. The second replacement gate 354 is not recessed.The second replacement gate dielectric layer 350 and the secondreplacement gate 354 may be formed, for example, as described inreference to the second replacement gate dielectric layer 150 and thesecond replacement gate 154 of FIG. 1H. In one version of the instantembodiment, a first replacement gate linewidth 356 of the recessed firstreplacement gate 352 is substantially equal to a second replacement gatelinewidth 358 of the second replacement gate 354. In an alternateversion, the first replacement gate linewidth 356 of the recessed firstreplacement gate 352 is 80 to 90 percent of the second replacement gatelinewidth 358 of the second replacement gate 354.

A channel length of the first MOS transistor 306 is longer than achannel length of the second MOS transistor 308, due to the recessedfirst replacement gate 352, which may desirably provide the first MOStransistor 306 with a threshold potential closer to a desired value thanthe second MOS transistor 308. Forming the first MOS transistor 306 withthe recessed first replacement gate 352 and without elevated LDD regionsmay provide a desired threshold value for the first MOS transistor 306while providing a desired cost and complexity of a fabrication sequencefor the integrated circuit 300.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

What is claimed is:
 1. An integrated circuit, comprising: a substratecomprising semiconductor material; a first metal oxide semiconductor(MOS) transistor, comprising a first replacement gate disposed on afirst dielectric layer and a first channel, wherein the first channelextends adjacent the first dielectric layer along both a horizontal anda vertical surface; and a second MOS transistor comprising a secondreplacement gate disposed on a second dielectric layer and a secondchannel, wherein the second channel extends adjacent the seconddielectric layer along a horizontal surface and not a vertical surface;in which: said first dielectric layer and said second dielectric layerhave substantially equal composition; said first replacement gate andsaid second replacement gate have substantially equal composition; andsaid first MOS transistor and said second MOS transistor have a samepolarity.
 2. The integrated circuit of claim 1, in which a first gatelinewidth of said recessed first replacement gate is substantially equalto a second gate linewidth of said second replacement gate.
 3. Theintegrated circuit of claim 1, in which a first gate linewidth of saidfirst replacement gate is 80 to 90 percent of a second gate linewidth ofsaid second replacement gate.
 4. The integrated circuit of claim 1, inwhich said first MOS transistor is part of a static random access memory(SRAM) circuit.
 5. The integrated circuit of claim 1, in which saidsecond MOS transistor is part of a logic circuit.
 6. The integratedcircuit of claim 1, in which said first replacement gate is recessed 2to 50 nanometers below said top surface of said substrate.
 7. Theintegrated circuit of claim 6, in which a surface of said substrateunder said first dielectric layer is substantially coplanar with asurface of field oxide under said first dielectric layer.
 8. Theintegrated circuit of claim 6, in which: said first MOS transistorfurther comprises elevated lightly doped drain (LDD) regions; and saidsecond MOS transistor further comprises LDD regions which are notelevated.
 9. The integrated circuit of claim 1, in which: said first MOStransistor further comprises elevated LDD regions; and said second MOStransistor further comprises LDD regions which are not elevated.
 10. Amethod of forming an integrated circuit, comprising the steps of:providing a substrate comprising semiconductor material; concurrentlyremoving a first sacrificial gate in a first MOS transistor and removinga second sacrificial gate in a second MOS transistor; concurrentlyremoving a first sacrificial gate dielectric layer in said first MOStransistor and removing a second sacrificial gate dielectric layer insaid second MOS transistor; forming an etch mask over said substrate insaid first MOS transistor so as to expose said substrate in said firstMOS transistor; removing semiconductor material from said substrate inan area for a recessed replacement gate in said first MOS transistor,such that an etched surface of said substrate is substantially coplanarwith an etched surface of field oxide adjacent to said etched surface ofsaid substrate, and such that semiconductor material is not removed fromsaid substrate in said second MOS transistor; concurrently forming afirst replacement gate dielectric layer in said first MOS transistor andforming a second replacement gate dielectric layer in said second MOStransistor; and concurrently forming a recessed first replacement gateon said first replacement gate dielectric layer and forming a secondreplacement gate on said second replacement gate dielectric layer; sothat said recessed first replacement gate is recessed below a topsurface of said substrate and said first MOS transistor and said secondMOS transistor have a same polarity.
 11. The method of claim 10, inwhich a first replacement gate linewidth of said recessed firstreplacement gate is substantially equal to a second replacement gatelinewidth of said second replacement gate.
 12. The method of claim 10,in which a first replacement gate linewidth of said recessed firstreplacement gate is 80 to 90 percent of a second replacement gatelinewidth of said second replacement gate.
 13. The method of claim 10,further comprising the steps: forming an epi-block layer over saidsecond MOS transistor so as to cover said substrate adjacent to saidsecond sacrificial gate and expose said substrate adjacent to said firstsacrificial gate; forming elevated LDD semiconductor regions adjacent tosaid first sacrificial gate by a selective epitaxial growth processwhile said epi-block layer is in place, so that elevated LDDsemiconductor regions are not formed adjacent to said second sacrificialgate; removing said epi-block layer; and subsequently implanting dopantsinto said elevated LDD semiconductor regions to form first LDD implantedregions into said substrate adjacent to said second sacrificial gate toform second LDD implanted regions, before said step of concurrentlyremoving said first sacrificial gate and said second sacrificial gate,so that said second LDD implanted regions are not elevated.
 14. Themethod of claim 10, in which said first MOS transistor is part of anSRAM circuit.
 15. The method of claim 10, in which said second MOStransistor is part of an logic circuit.
 16. A method of forming anintegrated circuit, comprising the steps of: providing a substratecomprising semiconductor material; forming an epi-block layer over asecond MOS transistor so as to cover said substrate adjacent to a secondsacrificial gate of said second MOS transistor and expose said substrateadjacent to a first sacrificial gate of a first MOS transistor; formingelevated LDD semiconductor regions adjacent to said first sacrificialgate by a selective epitaxial growth process while said epi-block layeris in place, so that elevated LDD semiconductor regions are not formedadjacent to said second sacrificial gate; removing said epi-block layer;subsequently implanting dopants into said elevated LDD semiconductorregions to form first LDD implanted regions into said substrate adjacentto said second sacrificial gate to form second LDD implanted regions, sothat said second LDD implanted regions are not elevated; concurrentlyremoving said first sacrificial gate and removing said secondsacrificial gate; concurrently removing a first sacrificial gatedielectric layer in said first MOS transistor and removing a secondsacrificial gate dielectric layer in said second MOS transistor;concurrently forming a first replacement gate dielectric layer in saidfirst MOS transistor and forming a second replacement gate dielectriclayer in said second MOS transistor; and concurrently forming a recessedfirst replacement gate on said first replacement gate dielectric layerand forming a second replacement gate on said second replacement gatedielectric layer.
 17. The method of claim 16, in which a firstreplacement gate linewidth of said recessed first replacement gate issubstantially equal to a second replacement gate linewidth of saidsecond replacement gate.
 18. The method of claim 16, in which a firstreplacement gate linewidth of said recessed first replacement gate is 80to 90 percent of a second replacement gate linewidth of said secondreplacement gate.
 19. The method of claim 16, in which said first MOStransistor is part of an SRAM circuit.
 20. The method of claim 16, inwhich said second MOS transistor is part of an logic circuit.